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Analysis and Design of Networks-on-chip Under High Process Variation (Hardcover) (Rabab Ezz-eldin &

Analysis and Design of Networks-on-chip Under High Process Variation (Hardcover) (Rabab Ezz-eldin & - image 1 of 1

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This book describes in detail the impact of process variation on Network-on-Chip (NoC) performance.  The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies.  The discussion includes variation in logic and interconnect, in order to evaluate the delay, throughput and leakage power variation with different NoC topologies.  The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns.  Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.

Genre: Technology, Computers + Internet
Sub-Genre: Electronics / Circuits / General, Computer Architecture, Electronics / General
Format: Hardcover
Publisher: Springer Verlag
Author: Rabab Ezz-eldin & Magdy Ali El-moursy & Hesham F. A. Hamed
Language: English
Street Date: December 23, 2015
TCIN: 50864821
UPC: 9783319257648
Item Number (DPCI): 248-12-1614

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