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Design-for-test and Test Optimization Techniques for Tsv-based 3d Stacked Ics (Reprint) (Paperback)
About this item
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
Genre: Technology, Computers + Internet
Publisher: Springer Verlag
Author: Brandon Noia
Street Date: September 9, 2016
Item Number (DPCI): 248-28-0406
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