:

product description page

Design-for-test and Test Optimization Techniques for Tsv-based 3d Stacked Ics (Reprint) (Paperback)

Design-for-test and Test Optimization Techniques for Tsv-based 3d Stacked Ics (Reprint) (Paperback) - image 1 of 1

About this item

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
Edition: Reprint
Genre: Technology, Computers + Internet
Format: Paperback
Publisher: Springer Verlag
Author: Brandon Noia
Language: English
Street Date: September 9, 2016
TCIN: 51636289
UPC: 9783319345345
Item Number (DPCI): 248-28-0406
If the item details above aren’t accurate or complete, we want to know about it. Report incorrect product info.

Guest reviews

Prices, promotions, styles and availability may vary by store & online. See our price match guarantee. See how a store is chosen for you.