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Concentrating on sequential logic design with emphasis on the detailed design of various Verilog HDL projects, each chapter includes numerous problems. These designs include the design module and test bench module which tests for correct functionality. The reader should have an adequate knowledge of number systems and number representations; various types of binary codes; minimization of switching functions, including Boolean algebra, algebraic minimization, Karnaugh maps, and mapentered variables; the Quine-McCluskey algorithm; the Petrick algorithm; combinational logic; and storage elements. A detailed introduction to Verilog is presented.