How Transistor Area Shrank by 1 Million Fold - by Howard Tigelaar

Book Synopsis

​This book explains in layman's terms how CMOS transistors work. The author explains step-by-step how CMOS transistors are built, along with an explanation of the purpose of each process step. He describes for readers the key inventions and developments in science and engineering that overcame huge obstacles, enabling engineers to shrink transistor area by over 1 million fold and build billions of transistor switches that switch over a billion times a second, all on a piece of silicon smaller than a thumbnail.

From the Back Cover

This book explains in layman's terms how CMOS transistors work. The author explains step-by-step how CMOS transistors are built, along with an explanation of the purpose of each process step. He describes for readers the key inventions and developments in science and engineering that overcame huge obstacles, enabling engineers to shrink transistor area by over 1 million fold and build billions of transistor switches that switch over a billion times a second, all on a piece of silicon smaller than a thumbnail.

• Written from a process integration point of view, in language accessible to a wide variety of readers;
• Provides readers with an understanding of how transistors work, how they are built, and the equipment used to build them;
• Describes the incredible science and engineering that was developed to keep transistor scaling on a Moore's Law trajectory - (transistor area reduced by half every 2 to 3 years);
• Enables readers to understand the engineering choices and compromises made while scaling transistors ever smaller, with the constraints that they switch ever faster and use less and less power.

About the Author

Education: Ph.D. Physical Chemistry, U. of Illinois. Postdoctorate in Physics and Quantum Optics, U. of Arizona. Postgraduate courses in Solid State Physics at U. of Texas Dallas and U. of Texas Arlington.

8 years - Tigelaar Consulting, LLC. Wrote 150+ patent applications for Customer. Yield consultant to several major semiconductor companies. Technical advisor to 3 startup companies.

2 years - PDF Solutions: Senior consultant. Yield enhancement and SRAM layout.

26 years - Texas Instruments, Inc. Managed technical engineering groups. Developed manufacturing flows for next generation integrated circuits. 70+ US patents. 40+ publications in technical journals. TI Fellow.

4 years - Abbott Labs, Inc. Managed Technical Troubleshooting group that diagnosed and fixed production problems and customer problems with Abbott's diagnostic kits.

5 years - Rohm and Haas Co. Plastics Engineer, Developed production procedures for diagnostic reagents. Setup and managed the production facility for RIA diagnostic kits for Micromedic Systems, Inc., a subsidiary of Rohm and Hass Co. 1 patent.

Cofounder of Testchip Technologies, LLC. Developed automated software for testchip layout.